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YMF781
APL-1
Automobile sound PLayer-1
Overview
YMF781 (APL-1: hereinafter described as APL-1) is an LSI, integrating synthesizer, ADPCM decoder and a CPU for control in one chip. Various sounds used in common automobiles, motor cycles, and electric appliances, such as alarm sound, operation sound, and melody sound, and pseudo engine sound for an electric car can be generated with a little CPU load. A control CPU incorporated enables APL-1 control by a simple command (API) from the external host CPU. Note: For API, refer to the APL-1 API specifications.
Features
CPU is incorporated and enabling controls for synthesizer and other functions by the simple commands. Stereo hybrid synthesizer that can generate up to 64 voices simultaneously. Time change low pass filter function by AL (Analog Lite) synthesizer is built in. ADPCM and PCM stream playback is possible. The default tone for FM and Wave Table synthesizer is built in ROM, and registration of a tone to SRAM
is possible.
Speaker amplifier and equalizer circuit is built in. Stereo / monaural analog output terminal is equipped. Two control circuits for LED lighting are built in. The inspection function is APL-1 control interface
The synchronization with contents and compulsive control are also possible. built in as an external memory interface function.
Three interfaces are provided: Clock Sync Serial, Asynchronous Serial (UART) and Command Port (Mode, which identify commands by the changes of bus.) Power down function is built in. Input and output port Some terminals can be used as an Input/Output port, which can be controlled from the host CPU. Malfunction prevention function owing to the electrostatic noise and electromagnetic noise is built in. Core power supply 3.3V (3.0V to 3.6V) I/O power supply 3.3V and 5.0V are changed. 3.3V (3.0V to 3.6V) 5.0V(4.75V to 5.25V) Speaker amplifier power supply 3.3V (3.0V to 3.6V) 100pin plastic SQFP, pin lead plating with Pd-free (YMF781-SZ)
YMF781 CATALOG CATALOG No.: LSI-4MF781A3 2004.10
YMF781
Terminal Assignment
(P30)
SPOUT2 52
RDN
VDD
VSS
D10
D11
VDD
VSS
VDD
D12
D13
D14
D0
D8
D1
D9
D2
D3
D4
D5
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
D6
56
55
54
53
(P31) (P32) (P33)
CS0N CS1N CS2N A1 A2 A3 A4 A5 A6 A7 A17 A18 A19 VDD VSS VDD
51
SPOUT1
D15
VSS
D7
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
SPVSS SPVDD EQ3 EQ2 EQ1 AOR AOL VREF VSS VDD RSTN TRSTN TDI TCK TMS TDO TST1 TST0 VDD VSS VDD XO XI VSS SEL
(P34)
WRN
(P35) A21/A0 A20 A8 A9 A10 A11 A12 A13
(P36) LBN/LWRN
(P37) UBN/UWRN
LED1
LED2
RTSN
CTSN
VDDC
HSEL
SMODE
SWRN
SRDYN
SCLKN
(P00)
(P01)
(P10)
(P11)
(P20)
(P21)
(P22)
(P23)
(P24)
(P25)
< 100 pin SQFP Top View >
2
(P26)
IRQN
A14
A15
A16
VSS
VDD
TXD
RXD
VDD
VSS
PD
SDO
SDI
YMF781
Terminal Functions
Functions External memory Address bus 14 External memory Address bus 15 External memory Address bus 16 External memory Low byte enable External memory Upper byte enable Ground Power Supply (3.3V) LED output 1 LED output 2 Asynchronous Serial (UART) transmission request output Asynchronous Serial (UART) transmission request input Asynchronous Serial (UART) transmission output Asynchronous Serial (UART) reception input Power supply (3.3V) Ground Power supply (3.3V/5.0V) Power-down Serial interface selection (Asynchronous / clock sync) Clock sync serial mode selection (MSB/LSB first) Clock sync serial write enable Clock sync serial ready Clock sync serial clock Clock sync serial data output Clock sync serial data input Interrupt output Port selection (clock sync serial / port2) Ground X'tal connection X'tal connection Power supply (3.3V) Ground Power supply (3.3V) Test input terminal Normally, connect to the ground and use. Test input terminal Normally, connect to the ground and use. Test output terminal Normally, use without connection. Test input terminal Normally, connect to the power supply (VDD) and use. 37 TCK Ish Test input terminal Normally, connect to the power supply (VDD) and use. 38 TDI Ish Test input terminal Normally, connect to the power supply (VDD) and use. 39 TRSTN Ish Test input terminal normally, connect to the Ground and use. 40 RSTN Ish Hardware reset 41 VDD Power supply (3.3V) 42 VSS Ground 43 VREF AAnalog Reference Signal 44 AOL AO Analog Lch output or Lch+Rch output (monaural) 45 AOR AO Analog Rch output 46 EQ1 AEqualizer terminal 1 47 EQ2 AEqualizer terminal 2 48 EQ3 AEqualizer terminal 3 49 SPVDD Power supply for exclusive use of speaker (3.3V) 50 SPVSS Ground for exclusive use of speaker Note1: : CMOS output terminal, I: CMOS input terminal, Ish: Schmitt CMOS input terminal, A: Analog terminal Note2: The current value of the ( ) in the I/O (output type) indicates the output drive capability of its terminal. Note3: The power supply, VDDC can be switched to 3.3V or 5.0V. Note4: For the terminals without the description of "VDDC is used" in the table, VDD (only 3.3V) is used to drive it. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Terminal Name (Port) A14 A15 A16 LBN/LWRN (P36) UBN/UWRN (P37) VSS VDD LED1 LED2 RTSN (P00) CTSN (P01) TXD (P10) RXD (P11) VDD VSS VDDC PD HSEL (P20) SMODE (P21) SWRN (P22) SRDYN (P23) SCLKN (P24) SDO (P25) SDI (P26) IRQN SEL VSS XI XO VDD VSS VDD TST0 TST1 TDO TMS I/O (Output Type) O (4mA) O (4mA) O (4mA) O (4mA) O (4mA) O (4mA) O (4mA) O (4mA) Ish O (4mA) Ish Ish Ish Ish Ish Ish/O (4mA) Ish Ish/O (4mA) Ish O (4mA) Ish I O Ish Ish O Ish
VDDC is used VDDC is used VDDC is used VDDC is used
VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used VDDC is used
3
YMF781
No. Terminal Name (Port) I/O (Output Type) Function 51 SPOUT1 AO Speaker connection terminal 1 52 SPOUT2 AO Speaker connection terminal 2 53 VSS Ground 54 D15 Ish/O (2mA) External memory Data Bus 15 55 D7 Ish/O (2mA) External memory Data Bus 7 56 D14 Ish/O (2mA) External memory Data Bus 14 57 D6 Ish/O (2mA) External memory Data Bus 6 58 D13 Ish/O (2mA) External memory Data Bus 13 59 D5 Ish/O (2mA) External memory Data Bus 5 60 D12 Ish/O (2mA) External memory Data Bus 12 61 VDD Power Supply (3.3V) 62 VSS Ground 63 VDD Power Supply (3.3V) 64 D4 Ish/O (2mA) External memory Data Bus 4 65 D11 Ish/O (2mA) External memory Data Bus 11 66 D3 Ish/O (2mA) External memory Data Bus 3 67 D10 Ish/O (2mA) External memory Data Bus 10 68 D2 Ish/O (2mA) External memory Data Bus 2 69 D9 Ish/O (2mA) External memory Data Bus 9 70 D1 Ish/O (2mA) External memory Data Bus 1 71 D8 Ish/O (2mA) External memory Data Bus 8 72 D0 Ish/O (2mA) External memory Data Bus 0 73 VSS Ground 74 VDD Power Supply (3.3V) 75 RDN (P30) O (4mA) External memory Read Enable 76 CS0N (P31) O (4mA) External memory Chip Select 0 77 CS1N (P32) O (4mA) External memory Chip Select 1 78 CS2N (P33) O (4mA) External memory Chip Select 2 79 A1 O (4mA) External memory Address Bus 1 80 A2 O (4mA) External memory Address Bus 2 81 A3 O (4mA) External memory Address Bus 3 82 A4 O (4mA) External memory Address Bus 4 83 A5 O (4mA) External memory Address Bus 5 84 A6 O (4mA) External memory Address Bus 6 85 A7 O (4mA) External memory Address Bus 7 86 A17 O (4mA) External memory Address Bus 17 87 A18 O (4mA) External memory Address Bus 18 88 A19 O (4mA) External memory Address Bus 19 89 VDD Power Supply (3.3V) 90 VSS Ground 91 VDD Power Supply (3.3V) 92 WRN (P34) O (4mA) External memory Write Enable 93 A21/A0 (P35) O (4mA) External memory Address Bus 21/0 94 A20 O (4mA) External memory Address Bus 20 95 A8 O (4mA) External memory Address Bus 8 96 A9 O (4mA) External memory Address Bus 9 97 A10 O (4mA) External memory Address Bus 10 98 A11 O (4mA) External memory Address Bus 11 99 A12 O (4mA) External memory Address Bus 12 100 A13 O (4mA) External memory Address Bus 13 Note1: : CMOS output terminal, I: CMOS input terminal, Ish: Schmitt CMOS input terminal, A: Analog terminal Note2: The current value of the ( ) in the I/O (output type) indicates the output drive capability of its terminal. Note3: The power supply, VDDC can be switched to 3.3V or 5.0V. Note4: For the terminals without the description of "VDDC is used" in the table, VDD (only 3.3V) is used to drive it.
4
YMF781
Overview of the Operation
APL-1 includes the Synthesizer Core, the CPU for control and its peripheral circuit. The CPU controls most of the controls such as Synthesizer Core and Input/Output Port. Since the Synthesizer Core controls are all controlled by the built-in CPU, sound contents can be played by a simple command from the external. The sound contents are stored in the external ROM. Since the sound contents support formats in SMAF, SMAF/Phrase and SMAF/Audio, ROM data can be created by the development tool dedicated for APL-1. The firmware in the built-in CPU is stored in the external ROM and can be updated by the exchange of ROM, or by the download via the APL-1 Control Interface. Likewise, for the sound contents, it can be updated by the exchange of ROM, or by the download via the APL-1 Control Interface. APL-1 Control Interface: Clock Sync Serial, Asynchronous Serial (UART), is incorporated and can be selected by the terminal. (Mode 1)
Sound Contents Built-in CPU firmware Mobile phone PC Memory card Wireless communication Sound Contents APL-1 Speaker Output
Flash-ROM or ROM
VOL
Host CPU
Clock Sync Serial
Control CPU
Synthesizer Core MA-5
+
CPUI
VOL
VOL
EQ
UART
DAC
Interface Device
AMP Line out
Note: A configuration diagram, which mode 1 is selected as an APL-1 Control Interface, is shown.
The download of the sound contents and the update of the APL-1 firmware are normally performed via the host CPU. When it is difficult to mount a download function in host CPU, the download of sound contents and the update of the firmware can be performed directly by using the asynchronous serial (UART). However, the connection destination is restricted to PC Asynchronous Serial (UART).
5
YMF781
Block Diagram
A1-A20 D0-D15 RDN (P30) WRN (P34) CS0N (P31) CS1N (P32) CS2N (P33) A21/A0 (P35) LBN/LWRN (P36) UBN/UWRN (P37) IRQN RTSN (P00) CTSN (P01) TXD (P10) RXD (P11) SEL HSEL (P20) SMODE (P21) SWRN (P22) SRDYN (P23) SCLKN (P24) SDO (P25) SDI (P26)
APL-1 Control Interface
External Memory Interface
Control CPU
RSTN
Synthesizer Core MA-5
DAC
Boot ROM Work RAM Timer WDT Others
VOL VOL EQ
EQ3 EQ2 EQ1 SPOUT1 SPOUT2 SPVDD SPVSS AOR AOL
+
XO
Power-down Controller
Overview of the block
The overview function of each block and the flow of a signal are explained. Control CPU The Control CPU controls APL-1 in all as well as the Synthesizer Core controls such as a sequencer function. Synthesizer Core Hybrid Synthesizer Core equivalent to MA-5, which is a synthesizer LSI for mobile phone. The synthesizer performs play of the sound contents, LED controls, etc. External Memory Interface The interface connects APL-1 to the external memory. Accessible memory space is up to 8MByte. (CS0N:ByteCS1N:ByteCS2N:Byte.) SRAM with the specification of byte access is necessary. From P30-P37 can be used as the output port when only one external ROM is used. APL-1 Control Interface APL-1 is controlled through the APL-1 Control Interface. Mode 1 and Mode 2 can be selected according to the settings of SEL terminal. In Mode , Clock Sync Serial and Asynchronous Serial (UART) can be switched and used by the HSEL terminal. In Mode 2, Asynchronous Serial (UART) and command port (A mode, which identify command by the change of data that inputted into P20-P26) can be used at the same time. P01 and P11 can be used as input port, and P00 and P10 can be used as output port, depending on the settings. Timing Generator Clocks used in the APL-1 are generated. Power-down Controller The controller controls APL-1 in the power-saving mode. Boot ROM, Work RAM, Timer, WDT, etc. The peripheral devices of the Control CPU in the APL-1.
6
TST0-TST1 TMS TCK TDO TDI TRSTN
PD
LED1 LED2
VREF
VOL
XI
Timing Generator
YMF781
Electrical Characteristics
Absolute Maximum Ratings tem
SPVDD terminal - Power supply Voltage (Speaker Amplifier section VDD terminal - Power supply Voltage VDDC terminal - Power supply Voltage SPOUT1, SPOUT2 terminal - Supplied voltage Analog Input Voltage Digital Input Voltage (1) (*1) Digital Input Voltage (2) (*2) Storage Temperature
Symbol
SPVDD VDD VDDC VINSP VINA VIND1 VIND2 TSTG
in.
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -50
ax.
6.0 4.2 7.0 SPVDD+0.3 VDD+0.3 VDDC+0.3 VDD+0.3 125
nit
V V V V V V V
Conditions: VSS = SPVSS = 0V (*1) Relevant terminals: RXD, CTSN, PD, HSEL, SMODE, SWRN, SCLKN, SDI, and SEL (When Port is used: P01, P11, and P20-P26) (*2) Relevant terminals: Other input terminals
Recommended Operating Conditions Symbol tem
SPVDD Operating Voltage (Speaker Amplifier section) VDD Operating Voltage VDDC Operating Voltage (compatible with 3.3V/5.0V Operating Ambient Temperature Conditions: VSS = SPVSS = 0V SPVDD VDD VDDC
in.
3.0 3.0 3.0 4.75 -40
yp.
3.3 3.3 3.3 5.0 25
ax.
3.6 3.6 3.6 5.25 85
nit
V V V V
TOP
Consumption Current tem
Normal operating Condition
Condition
VDD + VDDC SPVDD when in no output when in 8ohm, 330mW Output VDD + VDDC VDD + VDDC VDD + VDDC + SPVDD (*1)
in.
yp.
50 4 187 25 5 6
ax.
80 40 10 10 50
nit
mA mA mA mA mA A A
Stand-by 1 Mode Stand-by 2 Mode Shutdown Mode (TOP = 25) (TOP = 85) Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF (*1): VDD=VDDC=SPVDD=3.30V, and for Input terminals, VIL=VSS, VIH= VDD or VDDC
DC Characteristics tem
Symbol
Condition
in.
yp.
ax.
nit
V V V V V V V V V V A pF
Input voltage "H" level (1) *1) VIH1 0.70xVDDC Input voltage "L" level (1) (*1) VIL1 0.30xVDDC Schmitt Width (1) (*1) VSW1 0.15xVDDC Input voltage "H" level (2) (*2) VIH2 0.70xVDD Input voltage "L" level (2) (*2) VIL2 0.30xVDD Schmitt Width (2) (*2) VSW2 0.15xVDD Output voltage "H" level(1) (*1) VOH1 IOH = -2mA 0.8xVDDC Output voltage "L" level (1) (*1) VOL1 IOL = +4mA 0.2xVDDC Output voltage "H" level (2) (*2) VOH2 IOH = -2mA(*3) 0.8xVDD Output voltage "L" level (2) (*2) VOL2 IOL = +4mA(*3) 0.2xVDD Input Leak Current IL -10 10 Input Capacitance CI 15 Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF (*1) Relevant terminals: RXD, CTSN, PD, HSEL, SMODE, SWRN, SCLKN, SDI, and SEL (when Port is used: P01, P11, and P20-P26) (*2) Relevant terminals: Other Input Terminals (*3) Except for D0 to D15 terminal: IOH = -1mA, IOL = +2mA
7
YMF781
AC Characteristics
Input/Output level measurement conditions: VIH 0.75 x VDD unless otherwise specified VIL 0.25 x VDD VOH 0.75 x VDD VOL 0.25 x VDD or or or or 0.75 x VDDC 0.25 x VDDC 0.75 x VDDC 0.25 x VDDC
Reset and Clock Timing
RSTN, XI, and other input signals
tem
RSTN
Symbol
in.
yp.
ax.
nit
ms s s ms MHz ns ns ns ms ms MHz ns
"L" pulse width (When in power-up and in shut-down-cancel TRSTW 20 (When power supply and clock is in stable) 100 0 TRSTS RSTN (undefinedL) set-up time 0 3 TVSKW VDDVDDC power up time difference XI Frequency 1 / TXFREQ 6.144 XI Rising time and Falling time TXR , TXF 20 XI High time TXH 60 XI Low time TXL 60 XI Input delay time TXIIN 1 XI Input time TXIINW 1 Internal clock frequency 1/TCW 18.432 Input signals except XI Rising time and Falling time TR, TF 15 Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF Clock input to the XI terminal is necessary during the reset. Be sure to power VDD first when independent power supply is used for the supply of VDD and VDDC.
VDDC
The minimum of recommended operating voltage. 50%
TVSKW
VDD
50%
TRSTS RSTN
TRSTW
VIL= 0.25*VDD
TXIIN
TXIINW
XI
The reset width is defined from a point that VDDC reaches to the minimum of recommended operating voltage. RSTN input must be "L" level at the point where VDD reaches to 50%.
8
YMF781
TXR TXH XI TXFREQ TXF TXL
VIH= 0.75*VDD VIL= 0.25*VDD
TR Input Signals except XI
TF
VIH= 0.75*VDD or 0.75*VDDC VIL= 0.25*VDD or 025*VDDC
Clock Sync Serial Interface tem SCLKN frequency (Serial transfer speed) SCLKN High time SCLKN Low time SDI set-up time SDI hold time SDO output delay time SDO output hold time (*1) SRDYN output delay time (LH) (*2) Symbol 1 / TSFREQ TSH TSL TSIS TSIH TSOD TSOH TSRDD in. 220 220 0 75 200 110 300 yp. 1 ax. 2 nit MHz ns ns ns ns ns ns ns
Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF (*1) The last SDO output data is held until the next SCLKN falling edge is detected. (*2) Time to the High level in synchronization with SCLKN, when the first 1 bit is transmitted or received. The falling timing depends on the transmit/receive process of the internal Control CPU.
TSFREQ TSL SCLKN TSH
VIH= 0.75*VDDC VIL= 0.25*VDDC
TSIS
TSIH
SDI TSOD TSOH
SDO
TSRDD SRDYN
9
YMF781
Asynchronous Serial Interface UART tem Transfer Frequency (Baud rate: fixed to x16) RXD allowable frequency error (*1) Symbol 1 / TRXD in. 9 -2 yp. ax. 144 +2 nit kHz %
Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF (*1) In the case of 10 bits including the start bit and the stop bit.
External Memory Interface tem Data (D) Set-up time Data (D) Hold time Address (A) Output Delay time Control Signal Output Delay time (*1) Data (D) Output Delay time Data (D) Output turn-on time Symbol TDS TDH TAD TCTLD TDD TDT in. 10 10 yp. ax. nit ns ns ns ns ns ns
40 40 80 20
Conditions: TOP= -40 to 85, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF (*1) LBN/LWRN, UBN/UWRN, WRN, RDN, and CS*N
Internal Master Clock
MCK
TAD TAD
A[21:0]
TDD D[15:00]
(Output)
TDD
TDS D[15:00]
(Input)
TDT
TDH
LWRN, UWRN, WRN3clock or less
TCTLD
TCTLD
TCTLD LWRN, UWRN, WRN4clock or more TCTLD LBN, UBN, CS*N, RDN
TCTLD
TCTLD
Access time 2 to 9 clocks (variable)
Note that the output timing of LWRN, UWRN, and WRN differs in the access time of 3 clocks or less and that of 4 clocks or more.
10
YMF781
Analog Characteristics
Conditions: TOP=25, VDD=3.30V, SPVDD=3.30V
SP Amplifier tem Gain Settings (Fixed) Minimum load resistance (RL) Maximum Output Voltage Width (RL=8) Maximum Output Power (RL=8, THD+N1.0%) THD + N (RL=8, f=1kHz, 330mW output) Quiescent noise (A-filter: weighing filter) PSRR (f=1kHz) Amplitude Center voltage Differential Output Voltage Connectable maximum load capacitance to SPOUT1, SPOUT2 terminal (*) EQ Amplifier tem Possible Gain Setting Range Maximum Output Voltage Amplitude THD + N (f=1kHz) Quiescent noise (A-filter) Input Impedance Feedback resistor between EQ2-EQ3 SP Volume tem Volume Setting Range Volume Step Width THD + N (f=1kHz) EQ Volume tem Volume Setting Range Volume Step Width Quiescent noise (A-filter) Maximum Output Current Maximum Output Voltage Amplitude Output Impedance HP Volume tem Volume Setting Range Volume Step Width Quiescent noise (A-filter) Maximum Output Current Maximum Output Voltage Amplitude Output Impedance VREF tem VREF Voltage DAC tem in. Resolution Full scale Output Voltage THD+N (f= 1kHz) Quiescent noise (A-filter) Frequency Characteristics (f=50Hz to 20kHz) -3.0 (*) (*) A drop of the high range response owing to the aperture effect. yp. 16 1.65 -85 ax. 0.5 80 +0.5 nit Bit Vp-p dBV dB in. yp. 0.5xVDD ax. nit V in. -30 132 yp. 1 -90 1.65 300 ax. 0 nit dB dB dBV A Vp-p in. -30 132 yp. 1 -90 1.65 300 ax. 0 nit dB dB dBV A Vp-p in. -30 yp. 1 ax. 0 0.05 nit dB dB in. yp. 3.0 10 20 -90 ax. 30 0.05 nit dB Vp-p dBV M k in. yp. 2 8 5.5 480 0.03 -90 90 0.5xVDD 10 ax. nit times Vp-p mW dBV dB V mV pF
50 1000
(*): MAX 1000pF can be connected to the SPOUT1 terminal and the SPOUT2 terminal.
600
600
11
YMF781
MEMO
12
YMF781
Package Outline
13
YMF781
Notice
The specifications of this product are subject to improvement changes without prior notice.

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